Torus
Eight FPGA boards, 4ns apart
Up to 8 board positions in 2RU · 160×160 lanes of Layer 1 fabric · Flexible front I/O
LDA Torus is an FPGA compute platform with Layer 1 interconnect: up to eight FPGA boards in 2RU, with front I/O configured to the deployment and boards interconnected on top of it, either through the LDA Maze crosspoint switch or by direct cabling. Boards reach each other in nanoseconds, and the host CPU spends no cycles steering data between them.
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Different Industries, One Platform
Low latency, heavy compute, one chassis
What a Torus does depends on how its positions are populated. The same chassis serves execution paths measured in nanoseconds and workloads measured in teraflops.
Capital Markets
Market data arbitration, consolidated book building, load balancing, and multiple strategies operating on the same feed data. Layer 1 interconnect carries it from the front panel to any board, and board to board, with ultra-low latency.
HPC and AI
Compute-intensive FPGA and accelerator workloads. Mixed positions take GPUs and other PCIe accelerators alongside LDA FPGA boards, on a current-generation host: AMD EPYC™ 9005 series with up to 768 GB DDR5.
I/O Cards
Set the front panel
Three swappable card types, combined in any mix.
16 × 10/25G
SFP
Single-lane ports for the highest drop count.
8 cages → 32 links
QSFP
Break out to 40/100G trunks or 25G lanes.
8 cages → 64 links
QSFP-DD
Double-density cages — the most links per card.
Low-Latency Interconnect
Any point, any other point
How boards need to talk depends on the workload. A trading system may fan one feed out to every board at once; an HPC/AI build may mesh the same eight boards into a cluster over multiple 100G links. Torus serves both from the same parts: Layer 1 devices inside the chassis, plus direct cabling between boards.
3.6 – 4.2ns
Full roundtrip through the LDA Maze crosspoint switchMeasured internally, including a 7.5″ cable to the I/O card. The crosspoint's own distribution latency is estimated below 2ns. Every path stays inside the chassis, off the host CPU and off the front-panel links.
LDA Maze
25G crosspoint switch with up to 160×160 lanes (40× 100G links), carrying ARC6 connectors on both faces; utilized lanes scale with the ARC6 cabling fitted. Non-PCIe: it occupies one board position on either floor, centrally between the boards it serves. Maze HD, coming Q3, raises this to 288 lanes (72× 100G links).
Direct board-to-board
Optional direct interconnect between boards using special cabling.
LDA D6 Mark II
A PCIe form-factor full-mesh option at 44× 10G lanes per card, when a smaller 10G mesh will suffice.
Benefits
Up to 8 Board Positions in 2RU
Two full-size PCIe positions on the base 1RU floor, up to six additional mixed PCIe-size positions on the second, extending from 1RU as board count grows.
Simpler, Shorter Cabling
Interconnect happens inside the chassis, so inter-board traffic never consumes front-panel links. I/O cards face forward and span both floors.
Multiple Interconnect Options
LDA Maze crosspoint switch, direct board-to-board cabling, or LDA D6 Mark II full mesh; pick the one the build needs.
Nanosecond-Scale Layer 1 Fabric
3.6-4.2ns for a full roundtrip through the crosspoint switch, measured with a 7.5″ cable to the I/O card. No host-CPU PCIe hops in the path.
Sync to the Same Clock Source
All FPGA boards synchronize to a single clock source, with PPS inputs available. Each FPGA acts with predictable timing and no jitter.
FPGA Health Monitoring
Per-board health monitoring, suited to remote FPGA management across a deployed fleet.
LDA FPGA Boards
Populate the positions, define the system
Torus hosts LDA FPGA boards and other PCIe boards with common clock synchronization. Mixed positions also accept third-party accelerators, typically GPUs.
| Panther (SBM09P-3) | Orion HBM | Orion II | |
|---|---|---|---|
FPGA | AMD Virtex™ UltraScale+™ XCVU9P, -3 fastest grade | AMD Versal™ Premium HBM XCVH1582, -3 fastest grade | AMD Versal™ Premium VP1502 (default, -3); VP1552 / VP1402 / VP1202 compatible |
Memory | 4.6 Gbit (576 MB) 333 MHz SyncBurst™ SRAM; 9ns write / 12ns read access | 32 GB HBM2 on-chip + 64 GB LPDDR4 on board | 3.45 Gbit SyncBurst™ SRAM, <20 ns access + 8 GB LPDDR4 |
Connectivity | 4× QSFP28: 16× 25G / 16× 10G / 4× 100G / 4× 40G Ethernet channels | 9× Samtec AcceleRate® ARC6 sockets; 16 GTM lanes at 56 Gbps, channels characterized for 112 Gbps | 4× QSFP-DD cages (achievable rate depends on fitted FPGA) |
Host interface | PCIe® Gen3 x16 | PCIe® 4.0 x16, or 2× PCIe® 5.0 x8 bifurcated | PCIe® 4.0 x16, or 2× PCIe® 5.0 x8 bifurcated |
Slots / power | 1-slot passive (limited power) or 2-slot active-cooled, up to 225 W | Single- or dual-slot | Single- or dual-slot |
Typical role | Ultra-low-latency SyncBurst™ memory access (e.g. HFT) | High SerDes count (e.g. high-end switching) | Ultra-low-latency memory access and adaptable high-performance compute, scaled by FPGA choice |
Across LDA Platforms
Same components, different platforms
The fabric, boards and I/O cards in a Torus appear across the LDA platform line. Pick the chassis the deployment needs.
fabric
LDA Maze
Non-blocking full mesh Layer 1 fabric: 160 links of 10/25G, or up to 40 links of 40/100G.
platform
OmniX
Non-blocking full mesh Layer 1 fabric: 160 links of 10/25G, or up to 40 links of 40/100G.
platform
Unity
High-density multi-FPGA platform, shipping today.