Lynx

~0.65ns board path · VU2P FPGA with GTF transceivers · RX / TX taps integrated

Ultra-low-latency FPGA board. Shortest traces, integrated taps.
Lynx^TM pairs the AMD Virtex™ UltraScale+™ VU2P FPGA and its GTF transceivers with a board optimized around them — shortest-possible traces, soldered reduced-size SFPs, and full RX and TX tapping on every link.

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Front I/O options

Three front I/O boards, one mainboard.

Interchangeable front I/O boards mount belly-to-belly to the FPGA mainboard over six Samtec® Micro Blade connectors. Pick the optics your fabric needs; the latency profile follows. SFP I/O boards are available with single-mode or multi-mode optics. Two ARC6-16 connectors add 16 more links, accessible through LDA expansion I/O cards.

12x SFP without taps

~0.65ns total avg path
direct LC attach
Module latency included

12x SFP with taps

~0.77ns total avg path
24 tap channels (12 RX + 12 TX)
Module latency included

6x QSFP with taps

~0.51ns avg, board path
24 links · 48 tap channels
Module latency not included

Measured latency

Measured board-path latency, per front I/O option.

Board-path latency by front I/O option, receiver and transceiver, top and bottom mount. Fiber module latency included on SFP options; not included on QSFP.

QSFP with taps

Fiber module latency NOT included

RT/TX	Mounting	Minimum	Average	Maximum
Receiver	Top	0.40ns	0.50ns	0.62ns
Receiver	Bottom	0.40ns	0.50ns	0.64ns
Transceiver	Top	0.46ns	0.52ns	0.62ns
Transceiver	Bottom	0.46ns	0.52ns	0.60ns

SFP with taps

Fiber module latency included

RT/TX	Mounting	Minimum	Average	Maximum
Receiver	Top	0.72ns	0.76ns	0.80ns
Receiver	Bottom	0.72ns	0.76ns	0.82ns
Transceiver	Top	0.74ns	0.78ns	0.82ns
Transceiver	Bottom	0.74ns	0.78ns	0.84ns

SFP without taps

Fiber module latency included

RT/TX	Mounting	Minimum	Average	Maximum
Receiver	Top	0.60ns	0.64ns	0.72ns
Receiver	Bottom	0.60ns	0.66ns	0.76ns
Transceiver	Top	0.62ns	0.64ns	0.70ns
Transceiver	Bottom	0.62ns	0.66ns	0.70ns

ARC6 connectors

RT/TX	Minimum	Average	Maximum
RX	0.14ns	0.24ns	0.32ns
TX	0.14ns	0.22ns	0.33ns

Note:

QSFP interfaces require transceiver modules, which add a small amount of latency; SFP options attach LC fiber directly to on-board modules with no additional latency.

Benefits

Mechanical

Two-slot ¾-length PCI form-factor-compliant FPGA board

PCIe

Gen 4 ×8. Banks 224, 225

Tap

Four miniature multi-mode fiber transceivers, 12 transmit channels each. 48 tap channels total via four MPO12 fiber cables. Up to 100 m transmission.

Clocking

Three SI5397 Quad PLL jitter attenuators. Up to 12 synchronous channels; all attenuator inputs connected to FPGA GPIOs for maximum flexibility. All used SerDes quads reference clock 0 and 1 connected to jitter attenuators.
25 MHz 0.28 ppm TCXO connected to FPGA as a sync reference for jitter attenuators.
100 MHz, 250 MHz LVDS 50 ppm clocks connected to FPGA.

Configuration

1 Gbit QSPI flash with BMC direct programming. Xilinx JTAG.

USB

Internal 2-port USB hub connected to BMC and FT4232 Xilinx JTAG.

Power

Max 200 W

GTF Banks

Left-side banks: 125, 127, 128, 130, 131, 133. Ultra-low-latency proprietary I/O cards.
Right-side banks: 227, 228, 229, 230. Two ARC6-16 connectors located very close to the FPGA under the heatsink.

Front Panel Options

I/O card options for left-side banks:

12 SFP with taps on RX and TX. Tap penalty ~120 ps.
12 SFP without taps.
6 QSFP slots with taps on RX and TX. Tap penalty ~150 ps.

Additional Connectivity

I/O card options for right-side banks:

2× QSFP-DD PCIe low-profile form-factor card. Any cable length based on customer order.
4× QSFP PCIe full-height, half-length. Any cable length based on customer order.
Version with taps made upon request.

Management

LDA standard BMC for board management. Transceiver management and monitoring, CLI, Python and Go API for external access, board health monitoring, VCCINT voltage control*.

Note:

*VCCINT voltage control allows overvolting the VU2P FPGA. Board warranty is void if this function is used.

LDA Platforms

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