Benefits
Seamless integration
Provides an easy-to-use interface for existing code while offering an instant latency reduction.
Stability
This core provides IP-level Synchronous Ethernet support with jitter attenuators, ensuring timely and stable data transmission while improving signal reliability.
Flexibility
Available as both 32-bit (10 GbE) and 128-bit (40 GbE) cores. It allows for seamless integration with existing systems designed for conventional hard or soft Ethernet IP interfaces.
Unparalleled efficiency
Extremely efficient use of FPGA resources.
Specifications
| 10GbE | 40GbE | |
|---|---|---|
IP Core Interfaces | 16-bit AXI Streaming interface running at 644MHz 16-bit RX PCS bus for ultra-low latency parsing of received data | 64-bit AXI Streaming interface running at 644MHz 64-bit RX PCS bus for ultra-low latency parsing of received data |
Round Trip Latency | 21.8 nanoseconds, Including AMD FPGA Transceivers | 45.6 nanoseconds, Including AMD FPGA Transceivers |
FPGA Resource Utilization (per MAC/PCS core): *Measured on VU9P FPGA | 1020 CLB LUTs 1050 CLB Registers | 3850 CLB LUTs 3300 CLB Registers |