LDA's 644 MHz 10 GbE | 40 GbE MAC/PCS is the lowest latency IP core on the market with a roundtrip latency of 21.8 | 45.6 ns.
Optimized for the HFT industry, it provides an interface for seamless integration into existing code resulting in instant latency reduction.
The core fully integrates the custom Xilinx GTY wrapper exporting only essential interfaces such as clocks, GTY SerDes inputs and outputs, and AXI streaming interfaces.
The core provides IP-level Synchronous Ethernet (jitter attenuators) support.
IP Core Interfaces
The 644 MHz FPGA core provides multiple user interfaces:
- 16-bit | 64-bit AXI Streaming interface running at 644 MHz
- 16-bit | 64-bit RX PCS bus for ultra-low latency parsing of received data
Latency Information
The roundtrip latency of the MAC/PCS core is 21.8 | 45.6 ns, including Xilinx FPGA transceivers.
The core provides a FULLY REGISTERED AXI Streaming user interface.
FPGA Utilization
Resource utilization* per MAC/PCS core:
- 1020 | 3850 CLB LUTs
- 1050 | 3300 CLB Registers
322.265MHZ 128-bit Mode
32-bit | 128-bit mode allows seamless integration into existing systems designed for conventional Ethernet IPs.