Reduce Latency Using Clock Synchronization
The standard way of network data processing in an FPGA with active receive and transmit logics has an implicit latency penalty. Incoming and outgoing FPGA logics have separate clocks, and a clock domain crossing (CDC) is required if received data influences the data that has to be sent.
It's not a problem unless you are aiming to cut as much latency as possible.
To bypass the CDC, we need a way to lock the transmit clock to the receive clock. It is not generally possible due to the “jittery” clock recovered by the FPGA transceiver from the incoming signal. However, if you use LDA FPGA boards, they are all equipped with multiple jitter attenuator chips that allow cleaning the clock to a point that it can serve as a reference clock for transmitting logic.
And since the receive signal clock, in reality, represents the reference clock of the data source, and you send data with the same clock, what you get as a result is your system working synchronously and in the same clock domain with the exchange.