Direct SerDes Access Technology
No matter which standard of serial communication you use, there is one common denominator: for the most part, all such standards use a CML differential interface. In other words, they share a common transport and, where you use one, you can use the other - given that parties sending and receiving the data know what they are doing.
Enter Direct SerDes Access (DSDA™): a proprietary technology for repurposing standard interfaces, such as PCI Express, into electrical level transport for other communication protocols allowing data transfer in whatever format works best in a given use case.
In an FPGA, all data comes and goes through Serializer/Deserializer (SerDes). So, PCIe communication with the host on the FPGA side first goes through SerDes and then is handled by PCIe IP Core. That's the status quo of FPGA. Why though? PCIe, after all, is also a serial protocol and given DSDA, can be treated as a transport for 10GbE, Aurora, Interlaken or 25GbE – whatever you need and whatever the hardware can handle.
This technology is the cornerstone of LDA Technologies' family of FPGA devices. Using DSDA, all LDA devices expose any I/O that an FPGA and board have to offer. One of its most significant advantages is that it allows FPGA boards to connect directly without a “CPU-in-the-middle” forming grids, stars or clusters: naturally supporting vertical and horizontal scaling up to the point of hyperscaling. And that's not all: thanks to DSDA and given FPGA's discrete (gated) architecture, we are only one IP Core away from using multiple FPGAs as a single massive one.
What are the benefits of dropping PCIe protocol communication from FPGA?
It allows users to:
- Reduce latency that is added by passing through PCIe
- Free the space that PCIe DMA core takes in the FPGA
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