LDA NeoTap

Innovative 10/25/40G tap aggregation and timestamping solution from LDA Technologies

Implemented using LDA's flagship NEO reconfigurable networking and development platform, the LDA NeoTap combines industry-leading timestamping and clock synchronization features provided by the FPGA, multiple ultra-low latency Layer 1 connectivity options, and software packet processing with its modern-day flexibility.

Flexible Layer 1 Connectivity

  • Active Layer 1: eliminate the need for a separate Layer 1 device and optical taps thus simplifying the infrastructure
  • 10G and 25G configurable Layer 1 support on all options with a 25G Layer 1 board option coming soon
  • NeoTap HardWire: specialized 10G/25G passive Layer 1 interconnect with hardwired port pairs. With uniform 1.8 ns latency across the ports with 100 ps variance, it's a perfect fit for exchanges and hosted infrastructures
  • Full signal regeneration (retiming) – much better signal quality than using taps

Industry-leading FPGA timestamping and synchronization:

  • 100 ps timestamp accuracy
  • Two fixed 40G ports; dynamically switchable speeds between 10G and 25G on remaining ports.
  • Advanced PPS synchronization with 1 Hz and 10 MHz support – No timestamp jitter within a second when 10 MHz signal is available
  • White Rabbit synchronization support: Industry-standard implementation from Orolia Networks
  • Fully coherent 10G and 40G timestamps – simpler latency analysis in modern infrastructures that involve market data in multiple speeds
  • Industry-standard 16-byte Ethernet trailer with EPOC timestamp and extra fields – propagated advanced latency calculation data such as PCS codes and 40G-specific performance fields
  • Extensive statistics and troubleshooting software to identify network issues
  • FPGA generates up to 4 VLAN-tagged 100G streams to the backplane or external devices

After processing on the FPGA, the incoming packets are VLAN-tagged, contain a timestamped Ethernet trailer and are combined into up to 4 100G streams. There are two possible device configuration options for further processing of this traffic.

NeoTap Standard: data processing and routing on the device through backplane

The Standard version of NeoTap device includes one or two 100G NICs and a powerful CPU to receive the data from the FPGA, transform and store it on the device, or forward to its final destination.

  • 16-core 3.7 GHz AMD EPYC Milan CPU for standard configuration
  • Up to 256 GB RAM for ultra-deep packet buffers
  • One or two PCIe 4.0 x16 100G NICs for up to 400 Gbps backplane
  • Multiple NIC options: Intel E810, Mellanox Connect-X6, etc.
  • Simple VLAN interface mode: work with front panel ports using standard Linux tools: ping, tcpdump, etc.
  • DPDK-based high-performance packet routing utility from LDA: receive data from front panel ports, aggregate and rebroadcast through another ports. Source code available for custom modifications: compression, packet manipulation, etc.
  • Third-party tools and libraries supported out of the box: all standard Linux and NIC drivers used

NeoTap Basic: no processing on the device itself – data delivered to an external capture system

This is the most cost-effective option for the customers who already invested in a good packet capture and processing infrastructure.

  • Up to 4x 100G streams delivered to external infrastructure directly from the FPGA
  • No further processing on the NeoTap device – basic, cost-efficient CPU for configuration only
  • No ability to rebroadcast through front panel ports
  • Currently, only 100G is supported for the FPGA's output data streams