LDA Revo

A specialized Layer 1 device designed to make the multi-line arbitration infrastructure "revolutionary" simple, LDA Revo receives and distributes data from multiple exchange lines to multiple downstream devices with a consistent latency of less than 2.6 nanoseconds.

The LDA Revo appliance features:

• 12x SFP+ ports for exchange connectivity
• 24x QSFPDD ports (12 port pairs) for downstream (FPGA board) connectivity
• 6x QSFPDD ports for housekeeping/management tasks or external timestamping/capture
• Configurable Layer 1 for SFP+ output
• Downstream interconnect with 2"-7" QSFPDD copper cables
• Internal tap aggregation and timestamping option with all LDA NeoTap features for capture and monitoring.

Device Connectivity

The device's SFP+ ports are strategically distributed in such a way as to be as close as physically possible to the fiber links coming from the exchange. At the same time, QSFPDD ports are grouped in the middle to ensure cables connecting to downstream devices are as short as physically possible.

The LDA Revo replicates data (at Layer 1) from 12 SFP+ ports to 12 downstream devices using 24 QSFPDD ports. QSFPDD ports are grouped in pairs, carrying 12 lanes (8+4) per pair, leaving 4 lanes of the second port unused.

Each incoming port connects to a single crosspoint switch providing ultra-low unified latency replication across all ports. LDA's unique approach of splitting replication between multiple smaller crosspoint switches allows for the elimination of any extra latency introduced by larger crosspoint switches and the longer traces needed to deliver data to/from them.

Six auxiliary management QSFPDD ports are intended for tap aggregation/compliance purposes. A copy of each SFP+ lane ingress/egress link is replicated to the management QSFPDD ports.

Deployment

A 4U setup includes two LDA Revo devices in the middle and two LDA Unity6 platforms with 6 customer FPGA boards each, one above and one below. This setup can take 24 (12 + 12) data lines from an exchange and distribute them between 12 FPGA boards with less than 2.6 ns latency across all ports.